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[ak4687] ms1307-e-00 2011/05 - 1 - general description the ak4687 is a stereo audio codec wi th 2-channel input selector and a line driver. the interfaces of adc/dac can accept up to 24bit i nput data and support asynchronous oper ation. the input range of the pre-amplifier, that supports 3ch stereo inputs, is selectable by exte rnal resistors. both the input stereo selector and output drivers support ground reference 2vrms in/output, making it possible to remove ac-coupling capacitors and reducing external parts. the ak4687 has a dynamic range of 99db for adc, 105db for dac. it is well suitable for digital recordi ng systems, digital tvs, blu-ray recorders and home theater systems. features ? asynchronous adc/dac operation ? 3:1 capless stereo line input selector ? 24bit stereo adc - 64x oversampling - sampling rate up to 48khz - linear phase digital anti-alias filter - s/(n+d): 83db - dynamic range, s/n: 99db - digital hpf for offset cancellation ? 24bit two stereo dac - 128x oversampling - sampling rate up to 192khz - 24bit 8 times digital filter - s/(n+d): 95db - dynamic range, s/n: 105db - de-emphasis filter ? high jitter tolerance ? external master clock input: 256fs, 384fs, 512fs 768fs (fs=32khz 48khz) 128fs, 192fs, 256fs 384fs (fs=64khz 96khz) 128fs, 192fs (fs=128khz ~ 192khz) ? 2 audio serial i/f (port1, port2) - master/slave mode (port1) - i/f format port2: msb, lsb justified (16/24 bit), i 2 s port1: msb, lsb justified (16/24 bit), i 2 s ? hardware / i 2 c-bus control ? operating voltage: - digital i/o and charge pump: 3.0v 3.6v - adc analog: 3.0v 3.6v - dac analog: 3.0v 3.6v ? package: 48pinlqfp ak4687 asynchronous stereo codec with capless stereo selector
[ak4687] ms1307-e-00 2011/05 - 2 - 2ch adc cvee cp cn lout rout mclk1 bick1 lrck1 sdto msn port1 2vrms hpf serial i/f 2vrms +/-50mvdc input pwad bit pdn1 pin mclk2 bick2 lrck2 sdti port2 2ch dac serial i/f sda/ain1 scl/ain0 control i/f a vdd1 vss1 a vdd2 vss2 dvdd vss3 vref1 charge pump de-em lin1 lin2 lin3 rin1 rin2 rin3 i2c vref2 pdn2 pdn1 lo li ri ro vss4 vss5 cad0/cks pwad/pwda bit pdn1/pdn2 pin pwda bit pdn2 pin ak4687 block diagram
[ak4687] ms1307-e-00 2011/05 - 3 - ordering guide ak4687eq -20 +85 c 48pin lqfp (0.5mm pitch) AKD4687 evaluation board for the ak4687 pin layout ro 37 lin1 36 38 lin3 39 nc 40 rin2 41 lin2 42 43 nc 44 rin1 45 nc 46 i2c 47 li 35 34 33 32 31 30 29 28 27 26 msn 1 sdto 2 lrck1 3 bick1 4 mclk1 5 pdn1 6 pdn2 7 mclk 2 8 bick2 9 10 sdti 11 23 22 21 20 19 18 17 16 15 14 13 dvdd nc nc top view sda/ain1 48 cad0/cks 12 24 25 scl/ain0 rin3 ak4687eq cp vss3 nc cn rout cvee lout test2 a vdd1 vss1 vss4 vss5 vss2 a vdd2 vref2 lo ri vref1 test1 lrck2
[ak4687] ms1307-e-00 2011/05 - 4 - pin/function no. pin name i/o function 1 msn i port1 master mode select pin. ?l?(connected to the ground): slave mode. ?h?(connected to dvdd) : master mode. 2 sdto o audio serial data output pin (for port1) 3 lrck1 i/o channel clock pin (for port1) 4 bick1 i/o audio serial data clock pin (for port1) 5 mclk1 i adc master clock input pin (for port1) 6 pdn1 i power-down mode for adc when ?l?, the adc is powered-down. 7 pdn2 i power-down mode for dac when ?l?, the dac is powered-down. 8 mclk2 i dac master clock input pin (for port2) 9 bick2 i audio serial data clock pin (for port2) 10 lrck2 i input channel clock pin (for port2) 11 sdti i audio serial data input pin (for port2) cad0 i cad address pin (i2c pin = ?h?) 12 cks i adc mclk speed select pin (i2c pin = ?l?) ?h?: mclk=768fs , ?l?: mclk=256fs 13 test1 i this pin must be connected to the ground 14 test2 i this pin must be connected to the ground 15 nc - this pin must be connected to the ground 16 nc - this pin must be connected to the ground 17 dvdd - digital power supply pin, 3.0v 3.6v 18 vss3 - digital ground pin, 0v 19 cp i positive charge pump capacitor terminal pin (for analog input/output) 20 cn i negative charge pump capacitor terminal pin (for analog input/output) 21 cvee o charge pump circuit negative voltage output pin (for analog input/output) 22 nc - this pin must be connected to the ground 23 rout o rch analog output pin 24 lout o lch analog output pin 25 vref2 o reference output pin connect to vss2 with a 1f low esr capacitor over all temperatures. 26 avdd2 - dac analog power supply pin, 3.3v 3.6v 27 vss2 - dac analog ground pin, 0v 28 vss5 - dac analog ground pin, 0v 29 vss4 - adc analog ground pin, 0v 30 vss1 - adc analog ground pin, 0v 31 avdd1 - adc analog power supply pin, 3.0v 3.6v 32 vref1 o reference output pin connect to vss1 with a 1f low esr capacitor over all temperatures. 33 ri o rch feedback resistor input pin 34 ro o rch feedback resistor output pin 35 lo o lch feedback resistor output pin 36 li o lch feedback resistor input pin 37 rin3 i rch input 3 pin 38 lin3 i lch input 3 pin 39 nc - this pin must be connected to the ground 40 rin2 i rch input 2 pin 41 lin2 i lch input 2 pin 42 nc - this pin must be connected to the ground 43 rin1 i rch input 1 pin 44 lin1 i lch input 1 pin 45 nc - this pin must be connected to the ground
[ak4687] ms1307-e-00 2011/05 - 5 - pin/function (continued) no. pin name i/o function 46 i2c i i 2 c pin ?h?= i 2 c control, ?l?= h/w control sda i/o control data pin (i2c pin = ?h?) 47 ain1 i analog input select pin (i2c pin = ?l?) scl i control data clock pin (i2c pin = ?h?) 48 ain0 i analog input select pin (i2c pin = ?l?) note: all digital input pins must not be left floating. absolute maximum ratings (vss1=vss2=vss3=vss4 =vss5=0v; note 1 ) parameter symbol min max units power supply dvdd avdd1 avdd2 -0.3 -0.3 -0.3 4.0 4.0 4.0 v v v input current (any pins except for supplies) iin - 10 ma digital input voltage (mclk1-2, pdn1-2, lrck1-2, sdti, bick1-2, sda, scl, msn, cad0 pins ) vind -0.3 dvdd+0.3 v analog input voltage (lin1-3, rin1-3 pins) vina -0.3 avdd1+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. vss1, vss2, vss3, vss4 and vss5 must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=vss3=vss4=vss5= 0v; note 1 ) parameter symbol min typ max units power supply ( note 2 ) dvdd avdd1 avdd2 3.0 3.0 3.0 3.3 3.3 3.3 3.6 3.6 3.6 v v v note 2. the avdd1, avdd2 and cvdd must be the same voltage. the voltage difference between dvdd and other voltages (avdd1, avdd2 and cvdd) must be less than 0.3v. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4687] ms1307-e-00 2011/05 - 6 - analog characteristics (ta=25 c; avdd1=avdd2 = dvdd= 3.3v; vss1=vss2=vss3 =vss4 =vss5 =0v; fs=48khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency = 20hz 20khz at fs=48khz, 20hz~40khz at fs=96khz; 20hz~40khz at fs=192khz, all blocks are synchronized, unless otherwise specified) parameter min typ max units pre-amp characteristics: feedback resistance rf 12 39 92 k input resistance ri 18 47 92 k output level lo / ro pins (adc=0dbfs) ( note 3 ) 1.82 1.91 2.00 vrms load resistance r l ( note 4 ) 18 k load capacitance c l ( note 4 ) 20 pf analog input (lin1-3, rin1-3pin) to adc analog input characteristics resolution 24 bits s/(n+d) (-1dbfs) fs=48khz - 83 db dr (-60db fs) fs=48khz, a-weighted - 99 db s/n (input off) fs=48khz, a-weighted - 99 db interchannel isolation ( note 5 ) - 100 db interchannel gain mismatch 0 - db gain drift 50 - ppm/ c power supply rejection ( note 6) 50 db dac to analog output (lout, rout pin) characteristics resolution 24 bits s/(n+d) (0dbfs) fs=48khz fs=96khz fs=192khz - - - 95 93 93 db db db dr (-60dbfs) fs=48khz, a-weighted fs=96khz, a-weighted fs=192khz, a-weighted - - - 105 105 105 db db db s/n (?0? data) fs=48khz, a-weighted fs=96khz, a-weighted fs=192khz, a-weighted - - - 105 105 105 db db db interchannel isolation - 100 db interchannel gain mismatch 0 - db dc offset (at output pin) ?5 0 +5 mv gain drift 50 - ppm/ c output voltage lout/rout= 2 x avdd2/3.3 1.85 2 2.15 vrms load resistance 5 k load capacitance (c1) 30 pf power supply rejection ( note 6) 62 db note 3. input range for adc full scale when the external input resistance is 47k , feedback resistance is 39k and input signal is 2.3vrms. note 4. r l or c l of figure 2. load resistance and capacitance when the output signal of the lo/ro pin is used for an external device. note 5. this value is the channel isolation fo r all other channels between lin1-3 and rin1-3. note 6. psr is applied to avdd1, avdd2 and dvdd with 1khz, 50mvpp.
[ak4687] ms1307-e-00 2011/05 - 7 - 470 2.2nf ana log out c1 lout/rout ak4687 figure 1. lineout circuit example adc li lin1 lo 0v r i r f r i r i 0v lin2 lin3 r l c l - + ak4687 figure 2. external circuit of pre - amp
[ak4687] ms1307-e-00 2011/05 - 8 - power supplies parameter min typ max units power supply current normal operation (pdn1 pin = pdn2 pin = ?h?) avvd1 avdd2 dvdd dvdd+avdd1+avdd2 power-down mode (pdn1 pin = pdn2 pin = ?l?; note 7 ) dvdd+avdd1+avdd2 3 11 13 27 1 - - - 40 20 ma ma ma ma a note 7. pdn1-2 and test1-2 pins are held at vss3, and all digital inputs including clock pins (mclk1-2, bick1-2, lrck1-2, sdti, sda, scl, msn and cad0 pins) are held at dvdd or vss3. however, the lrck and bick pins should be open since these pins become output state when the msn pin is fixed to dvdd. filter characteristics (ta=25 c; avdd1=avdd2= dvdd= 3.3v; fs=48khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 8 ) 0.1db -0.2db -3.0db pb 0 - - 21.1 21.7 18.8 - - khz khz khz stopband sb 28.5 khz stopband attenuation sa 73 db group delay ( note 10 ) gd 17 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response ( note 8 ) -3db -0.1db fr 1.0 7.1 hz hz dac digital filter: passband 0.05db ( note 9 ) -6.0db pb 0 - 24.0 21.7 - khz khz stopband ( note 9) sb 26.3 khz passband ripple pr 0.05 db stopband attenuation sa 64 db group delay ( note 10) gd - 24 - 1/fs de-emphasis filter (dem = on) de-emphasis error (dc reference) fs = 32khz fs = 44.1khz fs = 48khz - - - - - - ?1.5/0 ?0.2/+0.2 0/+0.6 db db db dac digital filter + analog filter: (dem = off) frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.2 0.3 1.0 - - - db db db note 8. the passband and stopband frequencies scale with fs. for example, 21.8khz at ?0.1db is 0.454 x fs (dac). the reference frequency of these responses is 1khz. note 9. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.4535fs(@ 0.05db), sb=0.546fs. note 10. the calculating delay time occurred at digital filteri ng. this time is from setting the input of analog signal to setting the 24bit data of both channels to the output regist er of port1. for dac, this time is from setting the 20/24bit data of both channels on input register of port2 to the output of analog signal.
[ak4687] ms1307-e-00 2011/05 - 9 - dc characteristics (ta= 25 c; avdd1=avdd2= dvdd= 3.3v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage (iout=-400 a) low-level output voltage (iout= -400 a(except sda pin), 3ma(sda pin)) voh vol dvdd-0.4 - - - 0.4 v v input leakage current iin - - 10 a switching characteristics (ta=25 c; avdd1=avdd2=cvdd = dvdd= 3.3v; c l = 20pf (except for sda pin), cb=400pf(sda pin)) parameter symbol min typ max units master clock timing frequency duty feclk declk 8.192 40 50 36.864 60 mhz % master clock 256fsn, 128fsd: pulse width low pulse width high 384fsn, 192fsd: pulse width low pulse width high 512fsn, 256fsd, 128fsq: pulse width low pulse width high 768fsn, 384fsd, 192fsq: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 8.192 0.37 0.37 12.288 0.37 0.37 16.384 0.37 0.37 24.576 0.37 0.37 12.288 18.432 24.576 36.864 mhz 1/fclk 1/fclk mhz 1/fclk 1/fclk mhz 1/fclk 1/fclk mhz 1/fclk 1/fclk lrck1timing (slave mode) duty cycle fsn duty 32 45 48 55 khz % lrck2timing (slave mode) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 32 32 128 45 48 96 192 55 khz khz khz % lrck1 timing (master mode) normal speed mode duty cycle fsn duty 32 50 48 khz % power-down & reset timing pdn pulse width ( note 11 ) pdn ? ? to sdto valid ( note 12 ) tpd tpdv 150 2640 ns 1/fs note 11. refer to the ? system reset? paragraph for the reset by pdn1 and pdn2 pins. note 12. after a rising edge of pdn1, the internal counter starts by divided clock of mclk and adc power down is released by a falling edge of cvee after 64/fs on lrck, then sdtio is output 528/fs later.
[ak4687] ms1307-e-00 2011/05 - 10 - parameter symbol min typ max units audio interface timing (slave mode) port2(dac) bick2 period bick2 pulse width low pulse width high lrck2 edge to bick2 ? ? ( note 13 ) bick2 ? ? to lrck2 edge ( note 13 ) sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tsdh tsds 81 20 20 20 20 10 10 ns ns ns ns ns ns ns port1 (adc) bick1 period bick1 pulse width low pulse width high lrck1 edge to bick1 ? ? ( note 13 ) bick1 ? ? to lrck1 edge ( note 13 ) lrck1 to sdto (msb) bick1 ? ? to sdto tbck tbckl tbckh tlrb tblr tlrs tbsd 324 128 128 80 80 80 80 ns ns ns ns ns ns ns audio interface timing (master mode) bick1 frequency bick1 duty bick1 ? ? to lrck1 edge bick1 ? ? to sdto fbck dbck tmblr tbsd -20 64fs 50 20 20 hz % ns ns control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 14 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 - 0 400 - - - - - - - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note 13. bick rising edge must not occur at the same time as lrck edge. note 14. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 15. i 2 c-bus is a trademark of nxp b.v.
[ak4687] ms1307-e-00 2011/05 - 11 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fsn, 1/fsd, 1/fsq lrck vih vil tbck tbckl vih tbckh bick vil clock timing (normal mode) tlrb lrck vih bick vil tlrs sdto 50% tvdd tbsd vih vil tblr tsds sdti vih vil tsdh audio interface timing lrck= lrck1, lrck2 bick= bick1, bick2
[ak4687] ms1307-e-00 2011/05 - 12 - lrck bick sdto tbsd tmblr 50% dvdd 50% dvdd 50% dvdd audio interface timing (master mode) tpd vil pdn tpdv sdto 50% dvdd vih power down & reset timing thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing
[ak4687] ms1307-e-00 2011/05 - 13 - operation overview system clock the ak4687 has two audio serial interfaces (port1 and port2) which can be operated asynchronously. the port2 is the audio data interface for dac, and th e port1 is for adc. at each port, the ex ternal clocks, which are required to operate the ak4687 in slave mode, are mclk1 (mclk2), lrck1 (lrck2) and bick1 (bick2). the mclk1 (mckk2) must be synchronized with lrck1 (lrck2) but the phase is not critical. the ak4687 has independent power-down function for adc and dac controlled by the pdn1 and pdn2 pins (or pwad and pwda bits). in i 2 c control mode, the ak4687 is in normal operation when pdn1pin=pdn2 pin= ?h? and pwad bit = pwda bit = ?1? ( table 1, table 3 ). in h/w control mode ( table 2, table 4 ), the ak4687 is in normal operation when pdn1 pin = pdn2 pin = ?h?. the ak4687 is automatically powered-down when mclk1 clock is stopped in master mode (msn pin = ?h?), or when mclk1 (mclk2), lrck1 (lrck2) and bick1 (bick2) are pulled-down in slave mode (msn pin = ?l?). in this case, th e adc output is ?0? data and dac output is pulled down to vss. the power-down state is released and the ak4687 starts opera tion when mclk1 is input in master mode (msn pin = ?h?), or when mclk1 (mclk2), lrck1 (lrck2) and bick1 (bick2) are input in slave mode (msn pin = ?l?). when the reset is released (pdn1/2 pin = ?l? ?h?), such as after power up the device, the adc/dac of ak4687 is in power down state until mclk1/2, lrck1/2 and bick1/2 is input. pdn1 pin pwad bit master mode: mclk1 slave mode: mclk1,lrck1 and bick1 adc stauts adc out l power down 0 h 0 power down 0 h 1 non-active power down 0 h 1 active power up adc output (: don?t care) table 1. system clock for adc (i 2 c control mode, port1) pdn1 pin master mode: mclk1 slave mode: mclk1,lrck1 and bick1 adc stauts adc out l power down 0 h non-active power down 0 h active power up adc output (: don?t care) table 2. system clock for adc (h/w control mode, port1) pdn2 pin pwda bit mclk2,lrck2 and bick2 dac stauts dac out l power down vss h 0 power down vss h 1 non-active power down vss h 1 active power up dac output (: don?t care) table 3. system clock for dac (i 2 c control mode, port2) pdn2 pin mclk2,lrck2 and bick2 dac stauts dac out l power down vss h non-active power down vss h active power up dac output (: don?t care) table 4. system clock for dac (h/w control mode, port2)
[ak4687] ms1307-e-00 2011/05 - 14 - master/slave mode the msn pin controls master/slave mode of the port1. the port2 supports slave mode only. in master mode, lrck1 and bick1 pins are output pins. in slave mode, lrck1 (lrck2) and bick1 (bick2) pins are input pins ( table 5 ). msn pin port1 (adc) bick1, lrck1 port2 (dac) bick2, lrck2 l input (slave mode) input (slave mode) h output ?l?(master mode) input (slave mode) table 5. master/salve mode port1 (adc) clock control in master mode (msn pin = ?h?), the required clock is mc lk1. the cks1-0 bits and th e cks pin select the clock frequency ( table 6 , table 7 ). the adc is in power-down state un til mclk1, bick1 and lrck1 are supplied. cks1 bit cks0 bit clock speed 0 0 256fs 0 1 384fs 1 0 512fs 1 1 768fs (default) table 6. port1(adc) master clock control (master mode, i 2 c control mode) cks pin clock speed l 256fs h 768fs table 7. port1(adc) master clock control (master mode, h/w control mode) in slave mode (msn pin = ?l?), required clocks are mclk1, bick1 and lrck1. the master clock (mclk1) must be synchronized with lrck1 but the phase is not critical. after exiting reset following power-up (pdn1 pin = ?l? ?h?), the adc of ak4687 is in power down state until mclk1, lrck1 and bick1 are input. the adc only supports normal speed mode (fs = 32k ~ 48khz). lrck1 mclk1 (mhz) bick1 (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 8. port1(adc) system clock example
[ak4687] ms1307-e-00 2011/05 - 15 - port2 (dac) clock control external clocks (mclk2, bick2 and lrck 2) must always be present whenever the dac is in normal operation (pdn pin = ?h? or pwda2 bit= ?1?). the master clock (mclk2) must be synchronized with lrck2 but the phase is not critical. mclk2 clock is used for interp olation filter and delta sigma modulator. during operation, dac is automatically reset and the analog output goes to 0v (typ) if mclk2, lrck2 and bick2 are stopped. this reset is released, and the dac starts operation when mclk2, lrck2 and bick2 ar e input again. the dac is in power-down mode until mclk2, bick2 and lrck2 are supplied. there are two modes for controlling the sampling speed of dac . one is the manual setting mode (acks bit = ?0?) using the dfs1-0 bits, and the other is auto setting mode (acks bit = ?1?). 1. manual setting mode (acks bit = ?0?) when the acks bit = ?0?, dac is in manual setting mode and the sampling speed is selected by dfs1-0 bits ( table 9 ). dfs1 bit dfs0 bit dac sampling speed (fs) 0 0 normal speed mode 32khz~48khz 0 1 double speed mode 64khz~96khz (default) 1 0 quad speed mode 128khz~192khz 1 1 not available - table 9. port2(dac) sampling speed (acks bit = ?0?, manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 256fs 384fs 512fs 768fs 64fs 32.0khz 8.1920 12.2880 16.3840 24.5760 2.0480 44.1khz 11.2896 16.9344 22.5792 33.8688 2.8224 48.0khz 12.2880 18.4320 24.5760 36.8640 3.0720 table 10. port2(dac) system clock example (normal speed mode @manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 128fs 192fs 256fs 384fs 64fs 88.2khz 11.2896 16.9344 22.5792 33.8688 5.6448 96.0khz 12.2880 18.4320 24.5760 36.8640 6.1440 table 11. port2(dac)system clock example(double speed mode @manual setting mode) lrck2 mclk2 (mhz) bick2 (mhz) fs 128fs 192fs 256fs 384fs 64fs 176.4khz 22.5792 33.8688 - - 11.2896 192.0khz 24.5760 36.8640 - - 12.2880 table 12. port2(dac) system clock example (quad speed mode @manual setting mode)
[ak4687] ms1307-e-00 2011/05 - 16 - 2. auto setting mode (acks bit = ?1?) when the acks bit = ?1?, dac is in auto setting mode and the sampling speed is selected automatically by the ratio of mclk2/lrck2, as shown in table 13 and table 14 . in this mode, the settings of dfs1-0 bits are ignored. mclk2 dac sampling speed (fs) lrck2 512fs, 768fs normal speed mode 32khz~48khz 256fs, 384fs double speed mode 64khz~96khz 128fs, 192fs quad speed mode 128khz~192khz table 13. port2(dac) sampling speed (acks bit = ?1?, auto setting mode) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 32.0khz 8.192 12.288 44.1khz 11.2896 16.9344 48.0khz 12.288 18.432 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - - - quad table 14. system clock example when mclk= 256fs/384fs, the ak4687 supports sampling rate of 32khz~96khz ( table 15 ). but, when the sampling rate is 32khz~48khz, dr and s/n will degrade as compared to when mclk= 512fs/768fs. mclk dr, s/n 256fs/384fs 102db 512fs/768fs 105db table 15. mclk frequency and dr, s/n (fs = 48khz) de-emphasis filter the dac of ak4687 includes a digital de-emphasis filter (tc=50/15 s) by iir filter. setting th e dem1 bit to ?1? enables the de-emphasis filter. refer to ?filter characteristics ? about the gain error when this filter is on. the de-emphasis filter is off in double speed mode (mclk2 = 256fs/38fs ) and quad speed mode (mclk2=128fs/192fs). the filter setting is executed in i 2 c control mode and dem bit controls on/off of the filter. ( table 17 ) dem bit de-emphasis filter 1 on 0 off (default) table 16. de-emphasis control (normal speed mode)
[ak4687] ms1307-e-00 2011/05 - 17 - digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz at fs=48khz and frequency response scales with sampling rate (fs). audio serial interface format each port1/2 can select audio interface format independently. the dif1 bit controls audio data format of the port1. the dif1-0 bits control the audio data format of the port2. in all modes the serial data is msb-first, 2?s complement format. the sdto pin is clocked out on the falling edge of bick1 and the sdti pin is latched on the rising edge of bick2. sdti input formats can be used for 16-24bit data by zeroing the unused lsbs. 1. port1 (adc) setting the msn pin and dif1 bit select fo llowing four serial data formats ( table 17 ). lrck1 bick1 mode msn pin dif1 bit sdto l/r i/o speed i/o 0 l 0 24/16bit left justified h/l i 48fs or 32fs i (default) 1 l 1 24bit, i 2 s l/h i 48fs i 2 h 0 24bit left justified h/l o 64fs o (default) 3 h 1 24bit, i 2 s l/h o 64fs o table 17. audio inte rface format (adc) 2. port2 (dac) setting the dif21-20 bits select following four serial data formats ( table 18 ). lrck2 bick2 mode dif21 bit dif20 bit sdti l/r i/o speed i/o 0 0 0 16bit, right justified h/l i 32fs i 1 0 1 24bit, right justified h/l i 48fs i 2 1 0 24bit, left justified h/l i 48fs i (default) 3 1 1 24bit, i 2 s l/h i 48fs i table 18. audio inte rface format (dac)
[ak4687] ms1307-e-00 2011/05 - 18 - lrck bick(64fs) sdto(o) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 14 0 15 8 7 1 14 0 15 8 7 lch data rch data don?t care don?t care 12 11 10 sdto-23:msb, 0:lsb; sdti-15:msb, 0:lsb figure 3. port1= mode0/2, port2=mode0 timing lrck bick(64fs) sdto(o) 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti(i) 1 22 0 23 8 7 1 22 0 23 8 7 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 4. port1= mode0/2, port2=mode1 timing lrck bick(64fs) sdto(o) 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23 22 23 sdti(i) 22 23 0 22 23 23:msb, 0:lsb lch data rch data don?t care 2 2 1 28 29 30 23 0 22 23 24 31 1 0 don?t care 2 21 28 29 30 0 figure 5. port1= mode0/2, port2=mode2 timing lrck bick(64fs) sdto(o) 0 1 2 3 22 23 24 25 0 0 1 sdti(i) 31 29 30 23 22 1 22 23 0 23:msb, 0:lsb lch data rch data don?t care 2 2 1 0 2 3 22 23 24 25 0 31 29 30 23 22 1 22 23 0 don?t care 2 21 0 1 figure 6. port1= mode1/3, port2=mode3 timing
[ak4687] ms1307-e-00 2011/05 - 19 - input selector the ak4687 has 3:1 stereo input selectors. ain1-0 bits control each input channel in i 2 c control mode, and ain1/0 pins control each selector in h/w control mode. ( table 19 ) ain1 bit ain0 bit input selector 0 0 lin1 / rin1 (default) 0 1 lin2 / rin2 1 0 lin3 / rin3 1 1 reserved table 19. adc input selector (i 2 c control mode) ain1 pin ain0 pin input selector l l lin1 / rin1 l h lin2 / rin2 h l lin3 / rin3 h h reserved table 20. adc input selector (h/w control mode) pre-amp and input att the input attenuation circuit is constructed by connecting input resistors (ri) to lin1-3/rin1-3 pins and feedback resistors (rf) between li/ri pin and lo/ro pin ( figure 7 ). the input voltage tolerance of the lo/ro pin is typically 1.91vrms. therefore, excessive inputs such as 2vrms or 4vrms to the lin1-3/rin1-3 pins via ri resistors must be attenuated to 1.91vrms by these ri and rf resistors. table 21 shows resistance exam ples of ri and rf. lin1 lin2 lin3 li lo pre-amp ri ri ri r f figure 7. pre-amp and input att input range ri (k ? ) rf (k ? ) att gain (db) lo/ro pin adc output (typ) 4vrms 47 20 -7.42 1.70vrms -1.0dbfs 2.2vrms 47 39 -1.62 1.82vrms -0.39dbfs 1vrms 47 82 +4.83 1.74vrms -0.78dbfs table 21. input att example
[ak4687] ms1307-e-00 2011/05 - 20 - charge pump circuit the internal charge pump circuit generates negative voltage (cvee) from cvdd voltage for analog input and output. the power up time of charge pump circuit is 1.3ms@48khz. when pwad and pwda bits = ?1?, the adc and dac are powered-up after the charge pump circuit is powered-up. the power-up conditions of the charge pump circuit are: i 2 c control mode ? pdn1 pin = ?h?, pwad bit = ?1? and mclk1, lrck1 an d bick1 (mclk1 only in master mode) are input. ? pdn2 pin = ?h?, pwda bit = ?1? and mclk2, lrck2 and bick2 are input. h/w control mode ? pdn1 pin = ?h? and mclk1, lrck1 and bick1 (mck1 only in master mode) are input. ? pdn2 pin = ?h? and mclk2, lrck2 and bick2 are input. pdn1 pin pwad bit master mode: mclk1 slave mode: mclk1,lrck1, bick1 pdn2 pin pwda bit mclk2, bick2, lrck2 cp status h 1 active x x x on x x x h 1 active on (: don?t care) table 22. charge pump power on conditions (i 2 c control mode) pdn1 pin master mode: mclk1 slave mode: mclk1, lrck1, bick1 pdn2 pin mclk2, bick2, lrck2 cp status h active x x on x x h active on (: don?t care) table 23. charge pump power on conditions (h/w control mode) dvdd charge pump cp cn vss3 vee 1uf 1uf negative power a k4687 (+) cb ca (+) figure 8. charge pump circuit note: connect a 1f low esr capacitor between cp an d cn pins, and vss3-vee pins respectively.
[ak4687] ms1307-e-00 2011/05 - 21 - analog input/output (lin1-3/rin1-3, lout/rout pins) power supply voltage for analog input/output is applied fr om a regulator for positive power and a charge-pump for negative power. the analog output is single-ended and centered on 0v (vss2). therefore, a capacitor for ac-coupling can be removed. the minimum load resistance is 5k . when the dac input signal level is 0dbfs, the output voltage is 2vrms. v soft mute the dac has a soft mute function. the soft mute operation is performed at digital domain. when the smute bit goes to ?1?, the input data is attenuated by - in 1024lrck cycle. when the smute bit returns to ?0?, the mute is cancelled and the attenuation level gradually changes to 0db in 1024 lrck cycle. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and the attenuation level returns to 0db in the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute bit attenuation 1024/fs 0db - lout/rout 1024/fs gd gd (1) (2) (3) notes: (1) in normal speed mode, the input data is attenuated to - ? in 1024lrck cycle. for exam ple, this time is 2048lrck cycles (2048/fs) in do uble speed mode, and 4096lrck cycle (4096/fs) in quad speed mode. (2) the analog output corresponding to the digital input has group delay, gd. (3) if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and the attenuation level returns to 0db in the same cycle. figure 9. soft mute function v system reset when power-up the ak4687, the pdn1 and pdn2 pins should be ?l? and changed to ?h? after all power supplies (dvdd, avdd1, and avdd2) are supplied. after this reset is released (pdn1 and pdn2 pins = ?l? : ?h?), all blocks are in power-down mode. this ensures that all internal registers reset to their in itial values. adc internal circuit, control registers for adc (addr: 01h-02h) and pwad bit are reset by pdn1 pin = ?l?. dac internal circuit, control registers for dac (addr: 03h) and pwda bit are reset by pdn2 pin = ?l ?. when both pdn1 and pdn2 pins are ?l?, all blocks, resisters and charge pump are powered-down. in h/w contro l mode, register settings are ignored and the power-down controls by pdn1 and pdn2 pins are available.
[ak4687] ms1307-e-00 2011/05 - 22 - power on/off sequence the adc and dac blocks of the ak4687 are placed in powe r-down mode by bringing the pdn1 pin and pdn2 pin to ?l? respectively and both digital filters are reset at the same time. the pdn1 pin = pdn2 pin =?l? also reset the control registers to their default values. in power-down mode, the dac outputs 0v and the sdto pin goes to ?l?. this reset must always be executed after power-up. in master mode, the adc starts operatio n on the rising edge of mlck1 after power-down mode is released by a status change of the pdn1 pin from ?l? to ?h?. in slave mode, when power down mode is released by a status change of the pdn1 pin from ?l? to ?h?, the adc starts operation on the rising edge of lrck1 after mlck1, lrck1 and bick1 are input. the dac starts operation on the rising of the lrck2, after power-down mode is released by a status change of the pdn2 pin from ?l? to ?h?, and mclk2, lrck2 and bick2 are input. the analog initialization cycle of adc starts after exiti ng the power-down mode. therefore, the output data, sdto becomes available after 2640 cycles of lrck1 clock. in case of the dac, an analog initialization cycle starts after exiting the power-down mode. the analog outputs are 0v during the initialization. figure 10 shows power-down and power-up sequence. the adc and dac can be powered-down individually by pwad and pwda bits. register values are not initialized by these bits. when pwad bit = ?0?, the adc output goes to ?l?. when pwda bit = ?0?, the dac output goes to 0v. as some click noise occurs, the analog output should be muted externally if the click noise influences system application. a dc internal state clock in mclk1,lrck1,bick1 mclk2,lrck2,bick2 a dc in (analog) a dc out (digital) dac internal state dac in (digital) dac out (internal status) power-down don?t care gd ?0?data power-down ?0?data gd (5) (5) (6) timea init cycle normal operation (3) gd normal operation gd (4) ?0?data ?0?data don?t care (2) pdn1 pin = pdn2 pin power (1) (7) 0v cvee 0v cvee pin timeb (9) (8) 0v 80% avdd2 vref1/2 pin figure 10. power-up/down sequence example
[ak4687] ms1307-e-00 2011/05 - 23 - notes: (1) the pdn1 and pdn2 pins should be changed from ?l? to ?h? after power up. ?l? time of 150ns or more is needed to reset the ak4687 . the pdn pins must be held to ?l? until all power supply pins are fed. after all powers are risen up, th e pdn1 and pdn2 pins should be set to ?h?. (2) charge pump circuit power-up: when mclk1/2, bick1/2 and lrck1/2 are input after the pdn1/2 pin = ?l? ?h?, the voltage on the cvee pin rises to cvee voltage approximately in 1.3msec@48khz. note: if the pwad and pwda bits are set to ?1?, or pdn1 and pdn2 pins are set ?h? ?l? when the charge-pump is power-on, adc and dac are initialized after the charge-pump circuit is powered-on. (3) the analog block of adc is initialized after exiting the power-down state. timea=528/fs (4) the analog block of dac is initialized after exiting the power-down state. in case of connecting a 1f to the vref2 pin, timeb is shown below. timeb= 6/fs x 8 x 2: normal speed mode timeb=12/fs x 8 2: double speed modd timeb= 24/fs x 8 x 2 quatruple speed mode inputting d/a data becomes available after the timeb period. (5) digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay (gd). (6) adc outputs ?0? data in power-down state. (7) charge pump circuit power-down (pdn1 pin = ?h? ?l? or no mclk1, bick1 and lrck1 inputs) and (pdn2 pin = ?h? ?l? or no mclk2, bick2 and lrck2 inputs) the cvee pin becomes 0v accord ing to a flying capacitor and internal re sistor. the internal resister is 50k ? (typ). therefore, when the cvee pin has a flying capacitor of 1f, the time constant is 50msec (typ). (8) it takes 2048/fs for vref1 stabilization after charge pump is powered-up. (9) it takes approximately 5msec (typ) until vref1/2 rise s up after power-down mode of adc/dac is released.
[ak4687] ms1307-e-00 2011/05 - 24 - serial control interface the ak4687 supports fast-mode i 2 c-bus system (max: 400khz). 1. data transfer in order to access any ic devices on the i 2 c bus, input a start condition first, fo llowed by a single slave address which includes the device address. ic devices on the bus compare this slave address with their ow n addresses and the ic device which has an identical address with the slave-address gene rates an acknowledgement. the ic device with the identical address executes either a read or a write operation. after the command execution, input a stop condition. 1-1. data change change the data on the sda line while scl line is ?l?. sda line condition must be stable and fixed while the clock is ?h?. change the data line condition between ?h? and ?l? only when the clock signal on the scl line is ?l?. change the sda line condition while scl line is ?h? only when the start condition or stop condition is input. scl sda data line stable : data valid change of data a llowed figure 11. data transfer 1-2. start condition and stop condition a start condition is generated by the tran sition of ?h? to ?l? on the sda line while the scl line is ?h?. all instructions are initiated by a start condition. a stop condition is generate d by the transition of ?l? to ?h? on sda line while scl line is ?h?. all instructions end by a stop condition. scl sda stop condition start condition figure 12. start and stop conditions
[ak4687] ms1307-e-00 2011/05 - 25 - 1-3. acknowledge an external device that is sending data to the ak4687 releas es the sda line (?h?) after receiving one-byte of data. an external device that receives data from the ak4687 then sets the sda line to ?l? at the next clock. this operation is called ?acknowledgement?, and it enables ve rification that the data transfer ha s been properly executed. the ak4687 generates an acknowledgement upon receipt of a start cond ition and slave address. for a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. for a read instruction, succeeded by generation of an acknowledgement, the ak4687 releases the sd a line after outputting data at the designated address, and it monitors the sda line condition. when the master side generates an acknowledgement without sending a stop condition, the ak4687 outputs data at the next address location. when no acknowledgement is generated, the ak4687 ends data output (not acknowledged). scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge figure 13. acknowledge on the i 2 c-bus 1-4. first byte the first byte which includes the slave-address is input after th e start condition is set, and a target ic device that will be accessed on the bus is selected by the slav e-address. the slave-address is configur ed with the upper 7-bits. data of the upper 6-bits is ?001001?. the next 1 bit is the address bit that selects the desi red ic (cad0 bit). set cad0 bit according to the cad0 pin setting (cad0 pin = ?l?: cad0 bit = ?0?, cad0 pin = ?h?: cad0 bit = ?1?). when the slave-address is inputted, an external device that has the identical device address generates an acknowledgement and executes commands. the 8 th bit of the first byte (lsb) is allocated as r/w bit. when the r/w bit is ?1?, a read instruction is executed, and when it is ?0?, a write instruction is executed. 0 0 1 0 0 1 cad0 r/w figure 14. the first byte
[ak4687] ms1307-e-00 2011/05 - 26 - 2. write operations set r/w bit = ?0? for the write operation of the ak4687. after receipt of the start condition and the first byte, the ak 4687 generates an acknowledge, and awaits the second byte (register address). the second byte consists of the address for control registers of ak4687. the format is msb first, and those most significant 3-b its are ?don?t care?. * * * a4 a3 a2 a1 a0 (*: don?t care) figure 15. the second byte after receipt of the second byte, the ak 4687 generates an acknowledge, and awaits the third byte. those data after the second byte contain control data. the format is msb first, 8bits. d7 d6 d5 d4 d3 d2 d1 d0 figure 16. byte structure after the second byte the ak4687 is capable of more than one byte write operation by one sequence. after receipt of the third byte , the ak4687 generates an acknowledge, and aw aits the next data again. the master can transmit more than one data word instead of terminating the wr ite cycle after the first data word is transferred. after the receipt of each data, the internal addres s counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 03h prior to generating a stop condition, the address count er will ?roll over? to 00h and the previous data will be overwritten. sda s t a r t a c k a c k s slave a ddress a c k register a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) figure 17. write operation
[ak4687] ms1307-e-00 2011/05 - 27 - 3. read operations set r/w bit = ?1? for a read operation of the ak4687. the master can read next address?s data by generating an acknowledge instead of terminat ing the write cycle after the receipt of the first data word. after the receipt of each data, the internal 3bits ad dress counter is incremented by one, and the next data is taken into next address automatically. if th e address exceeds 03h prior to generating stop condition, the address counter will ?roll ov er? to 00h and the previous data will be overwritten. the ak4687 supports two basic read operations: current address read and random read. 3-1. current address read the ak4687 contains an internal address counter that maintains the address of the last word accessed, incremented by one. therefore, if the last access (either a read or write) was to address ?n?, the next current read operation would access data from the address ?n+1?. after receipt of the slave address with r/w bit set to ?1?, the ak4687 generates an acknowledge, transmits 1byte data, which address is set by the internal addr ess counter, and increments the internal address counter by 1. if the master does not generate an acknowledge but generate stop condition, the ak4687 discontinues transmission sda s t a r t a c k a c k s slave a ddress a c k data(n) data(n+1) p s t o p data(n+x) a c k data(n+2) figure 18. current address read 3-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues start condition, slave address(r/w bit=?0?) and th en the register address to read. after the register address?s acknowledge, the master immediately reissues the st art condition and the slave address with the r/w bit set to ?1?. then the ak4687 generates an acknowledge, 1byte data and increments the internal ad dress counter by 1. if the master does not generate an acknowledge but generate the stop condition, the ak4687 discontinues transmission. sda s t a r t a c k a c k s s s t a r t slave a ddress word a ddress(n) slave a ddress a c k data(n) a c k p s t o p data(n+x) a c k data(n+1) figure 19. random read
[ak4687] ms1307-e-00 2011/05 - 28 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h powerdown/control 0 0 0 0 0 0 pwda pwad 01h ad input 0 0 0 0 0 0 ain1 ain0 02h ad clock 0 0 0 dif1 0 cks1 cks0 0 03h dac clock 0 acks dfs1 dfs0 dem dif21 dif20 smute note: for addresses from 04h to 1fh, data must not be written. all registers are initialized to their default valu es by setting the pdn1 and pdn2 pins to ?l?. adc is powered down by setting the pdn1 pin to ?l?. registers for adc (addr: 01h-02h) and pwad bit are initialized. dac is powered down by setting the pdn2 pin to ?l?. registers for dac (addr: 03h) and pwda bit are initialized. adc is powered down by setting the pwad bit to ?0?. however, registers for adc (addr: 01h-02h) are not initialized. dac is powered down by setting the pwda bit to ?0?. ho wever, registers for dac (addr: 03h) is not initialized. the bits defined as 0 must contain a ?0? value.
[ak4687] ms1307-e-00 2011/05 - 29 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down/control 0 0 0 0 0 0 pwda pwad r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 pwad: adc power-down control 0: power-down (default) 1: normal operation pwda: dac power-down control 0: power-down (default) 1: normal operation addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h ad input 0 0 0 0 0 0 ain1 ain0 r/w rd rd rd rd rd rd r/w r/w default 0 0 0 0 0 0 0 0 ain1-0: adc input selector control ( table 19 ) 00: lin1/rin1 (default) 01: lin2/rin2 10: lin3/rin3 11: reserved
[ak4687] ms1307-e-00 2011/05 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h ad clock 0 0 0 dif1 0 cks1 cks0 0 r/w rd rd rd r/w rd r/w r/w rd default 0 0 0 0 0 1 1 0 cks1-0: port1 (adc) clock control in master mode see table 6 . dif1: port1 audio format select see table 17 . addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h dac clock 0 acks dfs1 dfs0 dem dif21 dif20 smute r/w rd r/w r/w r/w r/w r/w r/w r/w default 0 1 0 0 0 1 0 0 smute: soft mute control for dac 0: normal operation (default) 1: lout/rout outputs soft-muted dif21-20: port2 audio format select see table 18 . dem: dac de-emphasis response control see table 16. dfs1-0: port2 (dac) sampling speed control see table 9 . dfs1-0 bits setting is ignored in auto setting mode (acks bit = ?1?). acks: port2 (dac) auto setting mode control 0: disable, manual setting mode 1: enable, auto setting mode (default) the mclk frequency is detected automatically when acks bit= ?1?. in this case, dfs1-0 bits settings are ignored. when acks bit = ?0?, dfs1 -0 bits select the sampling speed mode, and the mclk frequency is automatically detected in each mode.
[ak4687] ms1307-e-00 2011/05 - 31 - system design figure 20 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ak4687eq micro controller audio dsp1 analog in 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 msn sdto pdn2 mclk2 bick lrck sdti cad0 i2c nc lin1 rin1 nc lin2 rin2 nc lin3 rin3 test1 test2 nc nc dvdd vss3 cp cn cvee nc rout lout li lo ro ri vref1 avdd1 vss1 vss4 vss5 vss2 avdd2 vref2 lrck1 bick1 mclk1 pdn1 scl sd a reset and power down 1u 10u 0.1u + 10u 0.1u audio dsp2 + 47k 47k 47k 47k 47k 47k + 10u 0.1u 1u 1u analog out 39k 39k ( ? ) 1u ( ? ) ( ? ) ( ? ) 3.3v 3.3v 3.3v 3.3v 3.3v figure 20. typical connection diagram (i 2 c control mode, cad0 pin = ?l?, master mode) notes: (1) use low esr (equivalent series re sistance) capacitors for the capacitors with (*). when using polarized capacitors, the positive polarity pin should be connected to the cp or vref1/2 pin, and the negative polarity pin should be connected to the cvee pin. (2) vss1, vss2, vss3, vss4 and vss5 must be connected to the same analog ground plane. (3) digital input pins should not be allowed to float.
[ak4687] ms1307-e-00 2011/05 - 32 - ak4687eq mode setting audio dsp1 analog in 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 msn sdto pdn2 mclk2 bick lrck sdti cks i2c nc lin1 rin1 nc lin2 rin2 nc lin3 rin3 test1 test2 nc nc dvdd vss3 cp cn cvee nc rout lout li lo ro ri vref1 avdd1 vss1 vss4 vss5 vss2 avdd2 vref2 lrck1 bick1 mclk1 pdn1 ain0 ain1 reset and power down 1u 10u 0.1u + 10u 0.1u audio dsp2 + 47k 47k 47k 47k 47k 47k + 10u 0.1u 1u 1u analog out 39k 39k ( ? ? ? ? figure 21. typical connection diagram (h/w control mode, mclk=768fs, master mode) notes: (1) use low esr (equivalent series re sistance) capacitors for the capacitors with (*). when using polarized capacitors, the positive polarity pin should be connected to the cp or vref1/2 pin, and the negative polarity pin should be connected to the cvee pin. (2) vss1, vss2, vss3, vss4 and vss5 must be connected to the same analog ground plane. (3) digital input pins should not be allowed to float.
[ak4687] ms1307-e-00 2011/05 - 33 - 1. grounding and power supply decoupling the ak4687 requires careful attention to power supply and grounding arrangements. avdd1, avdd2 and dvdd are usually supplied from the system?s analog supply. if avdd1, avdd2 and dvdd are supplied separately, the power up sequence is not critical. vss1, vss2, vss3, vss4 and vss5 of the ak4687 must be connected to the same analog ground plane. system analog ground and digital ground should be wi red separately and connected together as close as possible to where the supplies are brought on to the printed circuit board. decoupling capacitors should be as near to the ak4687 as possible, with the small va lue ceramic capacitor being the nearest. 2. voltage reference inputs the differential voltage between avdd1 and vss1 sets the analog input range, and the differential voltage between avdd2 and vss2 sets the analog output range. vref1/vref2 are signal common of this chip. a 1f ceramic capacitor attached between the vref1 and vref2 pins eliminates the effects of high freq uency noise. no load current may be drawn from the vref1/vref2 pins. all signals, especially clocks, should be kept away from the vref1/vref2 pins in order to avoid unwanted coupling into the ak4687. 3. analog inputs the analog input is single-ended and supplied to the pre-amp via external resistors. select th e feedback resistance to make the pre-amp output match to the input range (typ. 1.91vrms) of the adc (lo and ro pins). the adc output data format is 2?s complement. the internal digital hpf removes the dc offset. the ak4687 samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for mu ltiples of 64fs. the ak4687 in cludes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs. 4. analog outputs the analog outputs are single-ended and centered around the vss2 (0v typ.) voltage. the output signal range is typically 2.0vrms (typ @avdd2=3.3v). the internal switched-capacito r filter (scf) and continuous-time filter (ctf) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. using a 1st-order lpf ( figure 22 ) can reduce noise beyond the audio passband. the output voltage is a positive full scale for 7fffffh (@ 24bit) and a negative full scale for 800000h (@24bit). the ideal output is 0v (vss) for 000000h (@24bit). the dc offset is within 5mv. l/r ou t 470 2.2nf ak468 7 2.0vrms (typ) analog out (fc = 154khz, gain = -0.28db @ 40khz, gain = -1.04db @ 80khz) figure 22. external circuit example1 5. attention to the pcb wiring lin1-3 and rin1-3 pins are the summing nodes of the pre-amp. attention should be given to avoid coupling with other signals on those nodes. this can be accomplished by making the wire length of the input resistors as short as possible. the same theory also applies to the li/ri pins and feedback resistors; keep the wire length to a minimum. unused input pins among lin1-3 and rin1-3 pins must be left open.
[ak4687] ms1307-e-00 2011/05 - 34 - package 1 12 48 13 7.0 9.0 0.2 7.0 9.0 0.2 0.22 0.08 48pin lqfp (unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.3 0.75 0.5 material & lead finish package molding compound: epoxy, halogen (br and cl) free lead frame material: cu lead frame surface treatment : solder (pb free) plate
[ak4687] ms1307-e-00 2011/05 - 35 - marking a k4687eq xxxxxxx 1 1) pin #1 indication 2) marking code: ak4687eq 3) date code: xxxxxxx (7 digits) date (yy/mm/dd) revision reason page contents 11/05/30 00 first edition revision history
[ak4687] ms1307-e-00 2011/05 - 36 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, a pplication circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the in corporation of these external circuits, app lication circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor au thorized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no resp onsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in wh ich its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disp oses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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